1. Field of the Invention
The present invention relates to an insulated gate semiconductor device. More particularly, the invention relates to a device structure for decreasing a transient voltage upon switching of a power semiconductor device having an MOS gate and for size reduction of an application system including a snubber circuit.
2. Description of the Background Art
FIG. 14 is a cross-sectional view of a conventional insulated gate semiconductor device. As an example, an insulated gate bipolar transistor (referred to hereinafter as an IGBT)having a trench MOS gate structure will be described herein.
In FIG. 14, the reference numeral 1 designates a p.sup.+ collector layer; 2 designates an n.sup.+ buffer layer; 3 designates an n.sup.- layer; 4 designates a p base layer; 5 designates an n.sup.+ emitter layer; 6 designates a trench; 7 designates a gate insulating film; 8 designates a gate electrode; 9 designates an emitter electrode; 10 designates a collector electrode; and 11 designates a channel region.
The operation of the IGBT is described below.
When a predetermined collector voltage V.sub.CE is applied between the emitter electrode 9 and the collector electrode 10 and a predetermined gate voltage V.sub.CE is applied between the emitter electrode 9 and the gate electrode 8, that is, the gate is turned on, then the channel region 11 is inverted to the n type to form a channel through which electrons are emitted from the emitter electrode 9 into the n.sup.- layer 3. The emitted electrons cause forward bias between the p.sup.+ collector layer 1 and the n.sup.- layer 3, and holes are emitted from the collector electrode 10 via the p.sup.+ collector layer 1 and n.sup.+ buffer layer 2 into the n.sup.- layer 3. The result is a great amount of reduction in the resistance of the n.sup.- layer 3 due to conductivity modulation, increasing the current capacity of the IGBT. A voltage drop between the collector and emitter of the IGBT at this time is referred to as an on-state voltage (V.sub.CE(SAT)).
To switch the IGBT from the on position to the off position, the gate voltage V.sub.GE having been applied between the emitter electrode 9 and the gate electrode 8 is reduced to zero or reverse-biased that is, the gate is turned off. Then the n-inverted channel region 11 returns to the p type, and the emission of electrons from the emitter electrode 9 stops. Thereafter, the electrons and holes accumulated in the n.sup.- layer 3 either move to the collector electrode 10 and emitter electrode 9, respectively, or recombine together to disappear.
In general, the on-state voltage of the IGBT is primarily determined by the substantial resistance of the n.sup.- layer 3 required to hold the breakdown voltage. One of the factors of the substantial resistance is the ability of an MOSFET in the IGBT to supply electrons. An IGBT including a narrow deep trench in a chip surface and an MOSFET on the side wall of the trench (referred to hereinafter as a trench gate structure IGBT) is constructed such that the electron supply ability of the MOSFET is enhanced by possibly reducing the spacing between unit cells. Thus, this structure is permitted to decrease the on-state voltage while holding the required breakdown voltage.
Japanese Patent Application laid-Open No. 63-224260 (1988) discloses another conventional insulated gate semiconductor device. In the disclosure, a conductive-modulation MOSFET includes vertical source and channel region arranged in parallel, with a linear hole current path formed in a base region to reduce the lateral resistance in the p base layer thereby preventing latch-up.
In the conventional IGBT as above stated the increase in switching rate increases di/dt at turn-off to increase a spike voltage.
FIG. 15 is a graph showing the spike voltage.
In FIG. 15, V.sub.CE indicates a power supply voltage, I.sub.C indicates a collector current, and .DELTA.V.sub.CE indicates the spike voltage.
To withstand the spike voltage, there arises a need for the thickness of the n.sup.- layer 3 which is required to hold the breakdown voltage. The increase in spike voltage with the increase in switching rate increases the thickness of the n.sup.- layer 3 and the on-state resistance. The trench structure causes a high current density and a large amount of power losses in the on position. The increase in switching rate increases the spike voltage, thereby increasing power losses at switching.
To prevent such disadvantages resulting from the spike voltage at turn-off, it has been a common practice to connect an external snubber circuit to the IGBT to prevent the spike voltage. However, an inductance of external interconnection lines is present in the external snubber circuit. When di/dt further increases because of the connection of the snubber circuit to the trench structure IGBT, the spike voltage proportional to the inductance of the external interconnection lines increases, and further increase in thickness of the n.sup.- layer 3 of the device is required to withstand the spike voltage.
The applied voltage and current density are high when the snubber circuit is connected to the trench structure IGBT, and a capacitor having a considerable capacitance is required to prevent the development of the spike voltage. If the device of the IGBT is reduced in size and has an increased capacitance, the total system including the snubber circuit is not reduced in size.
A vertical DMOSFET (referred to hereinafter as a VDMOS) as well as the trench structure IGBT requires the connection of the snubber circuit to prevent the breakdown due to the spike voltage. The capacitance of the capacitor of the snubber circuit increases with the increased capacitance of the VDMOS, and the total system including a power module employing the VDMOS and the snubber circuit is not reduced in size.
In a bridge circuit formed by the VDMOS, an unnecessary parasitic transistor operates in some cases to cause arm short-circuit of the bridge circuit, resulting in device breakdown. The increase in switching rate requires a power MOS for the bridge circuit to which an FR (fast recovery) diode is mounted to prevent the arm short-circuit, and the size reduction of the module is not achieved.